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Complete SDARS Receiver
Pin Description
PIN
1, 4, 8,
12–15, 23,
26, 27, 30,
31, 40
2, 3
5, 6
7
9
10, 11
16
17, 19, 37,
39
18, 20, 36,
38
21, 22, 34,
35
24
25
28
29
32
33
41, 42
43, 44
—
NAME
VCC_FE0, VCC_FE1,
VCC_FE2, VCC_BE1,
VCC_BE2, VCC_BE3,
VINANT, VCC_XTAL,
VCC_D, VCC_A,
VCC_FE3, VCC_VCO,
VCC_BE4
RFIN+, RFIN-
IFOUT+, IFOUT-
RFAGC_C
AGCPWM
IFIN+, IFIN-
VOUTANT
IF2IO-, IF2IO+,
IF2QO+, IF2QO-
IF2II-, IF2II+, IF2QI+,
IF2QI-
IOUT-, IOUT+,
QOUT+, QOUT-
XTAL
REFOUT
LOCK
CPOUT
VCCREG
VTUNE
I 2 CA2, I 2 CA1
SCL, SDA
Exposed Pad
FUNCTION
Power Supplies. Bypass to ground with capacitors as close to the pins as possible.
Differential RF Inputs. Accept RF input signal from the SDARS cabled antenna with a 50 ? to
100 ? balun.
Differential First IF Output. Connect an external SAW filter to the IF output.
RF AGC Power-Detector Output. Set the RF AGC attack and decay response times.
IF AGC Control Voltage Input. Input from the filtered PWM AGC control signal from the SDARS
channel-decoder IC.
Differential First IF Input
Overcurrent-Protected Unregulated DC Supply Output. Provides DC power supply to the
antenna module.
Differential Baseband DC Blocking Outputs.
IF2IO- = Inverting in-phase baseband output. AC couple to pin 18.
IF2IO+ = Noninverting in-phase baseband output. AC couple to pin 20.
IF2QO+ = Noninverting quadrature baseband output. AC couple to pin 36.
IF2QO- = Inverting quadrature baseband output. AC couple to pin 38.
Differential Baseband DC Blocking Inputs.
IF2II- = Inverting in-phase baseband input. AC couple to pin 16.
IF2II+ = Noninverting in-phase baseband input. AC couple to pin 19.
IF2QI+ = Noninverting quadrature baseband input. AC couple to pin 37.
IF2QI- = Inverting quadrature baseband input. AC couple to pin 39.
Differential I/Q Baseband Outputs.
IOUT- = Inverting in-phase baseband output.
IOUT+ = Noninverting in-phase baseband output.
QOUT+ = Noninverting quadrature baseband output.
QOUT- = Inverting quadrature baseband output.
Crystal Reference Input
Buffered System Clock Output. Provides clock signal to the SDARS channel-decoder IC.
Digital Logic Output to the System Controller. Indicates the lock status of the internal PLL.
VCO Charge-Pump Output
Regulated Supply Voltage for the VCO
High-Impedance VCO Tuning Input
I 2 C Input Signals. Define the MAX2140 I 2 C device address.
I 2 C-Compatible Programming Input. Connect to an I 2 C-compatible bus.
Exposed Paddle. Connect to ground.
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